III-V 4D Transistors

Recently, III-V gate-all-around (GAA) nanowire MOSFETs or III-V 3D transistors have been experimentally demonstrated by a top-down approach [1-2] , showing excellent scalability down to channel length (Lch) of 50nm. Although parallel integration of the InGaAs nanowires have been successfully demonstrated in Ref. [1] delivering high drive current per wire, the overall current drivability of the devices are still limited by the relatively large pitch of the nanowires. This limitation would become even more severe with further down-scaling of the nanowire width (WNW) and height (HNW). One elegant solution to improve current drivability is through vertical stacking of nanowires, which has been demonstrated on Si platform [3] . In this work, we have developed a top-down fabrication process to create vertical (normal to the wafer) and lateral (parallel to the wafer) InGaAs nanowire arrays. We call this new type of nanowire devices III-V 4D transistors to distinguish them from III-V 3D transistors [1-2] which has only one vertical layer and multiple lateral wires. Furthermore, InGaAs GAA nanowire MOSFETs with 3×4 nanowire array has also been demonstrated for the first time.